The present invention relates to direct memory access (DMA) systems.
Direct memory access is a way of transferring data between a peripheral device and a memory. During direct memory access transfer, the central processing unit (CPU) is idle and does not have control of the memory buffers. A direct memory access controller takes over the buses to manage the transfer directly between the peripheral device and the memory.
Typically, the CPU initializes the DMA by sending the starting address of the memory block where the data is available or the data is to be stored, a count value indicating the length of the memory block, a control specifying the mode of transfer such as read or write, and a control to start the DMA transfer. The DMA controller stores the starting address in a buffer address register, the count in a buffer length register, and the control information in a control register.
In the DMA transfer, the DMA controller uses DMA request lines from a peripheral device to the DMA controller and DMA acknowledgement lines from the DMA controller to the peripheral devices. A peripheral device sends the DMA request to the DMA controller, and when the peripheral device receives the DMA acknowledgement, puts data on a data bus for a write, or captures data from the data bus for a read. The peripheral unit can, in this way, communicate with the memory through the data bus for direct transfer between the units while the CPU is momentarily disabled.
For each datum that is transferred, the DMA increments its address register and decrements the word count register. If the word count does not reach zero, the DMA checks the DMA request line from the peripheral. For so-called "burst mode" devices, the line may remain active as the previous transfer is completed. A second transfer is then initiated, and the process continues until the entire block is transferred. Alternately, the DMA request may be negated and then re-asserted somewhat later. In this case, the DMA disables the bus request line so that the CPU can continue to execute the program. When the peripheral device requests data transfer, the DMA requests the data bus again. If the count register reaches zero, the DMA stops any further transfer and removes the bus request. It also informs the CPU of the termination. The CPU can read the count register. A zero value of the count register indicates that all data in the buffer was transferred successfully.
Some DMA controller systems use list entries in memory rather than having the CPU unit write the buffer information into the DMA controllers. The list entry typically includes the starting address and count of a buffer, also located in the memory. The CPU can initialize the DMA by putting the location of the list entry into a list address register. The DMA controller then loads the address contained in the list entry to a buffer address register, and the count contained in the list entry into a buffer length register. Additionally, the list entry can include a link to another list entry, which allows for buffers arranged in a linked list or buffer ring.
The DMA controller may have more than one channel. Each channel has its own address register and word count register within the DMA controller. Recently, the number of peripheral devices typically integrated with a microprocessor has increased. For this reason, it is undesirable to have a DMA channel for each of the input-output (I/O) devices. Heath et al. U.S. Pat. No. 4,901,234, entitled "Computer System Having a Programmable DMA Controller," describes a system in which the number of peripherals greater than the number of DMA channels can have DMA access. Some of the DMA channels are dedicated to certain peripherals, while others, termed programmable DMA channels, are shared by the remaining peripherals. Each peripheral having DMA access has a channel priority value. When the peripheral wants DMA access, it transmits the channel priority value onto an arbitration bus. A disadvantage of this system is that this DMA arbitration system is somewhat complicated.
It is desired to have an improved DMA controller system that avoids some of the problems in the prior art.